With advances in CMOS integrated circuit technologies, operating speeds of integrated circuits have been remarkably enhanced. Accordingly, there is a demand for improvement of a clock signal for driving the integrated circuits including the need for operation of the clock signal at higher frequencies. The biggest problem resulting from the increase in clock frequency is a clock skew that occurs between an external clock signal and an internal clock signal. Clock skews cause errors in operation. Feedback correcting circuits such as phase locked loop (PLL) circuits and delay locked loop (DLL) circuits have been used to generate clock signals with minimized clock skew. However, a lock time of several clock cycles is needed to achieve phase lock. To shorten this lock time, a synchronous mirror delay (SMD) circuit has been proposed. The SMD circuit typically generates an internal clock signal synchronized with an external clock signal in two cycles.
A block diagram of a prior art synchronous mirror delay circuit is illustrated in FIG. 1. Waveform diagrams of input and output signals in each unit for generating an internal clock signal are illustrated in FIG. 2A through FIG. 2F.
Referring to FIG. 1, a synchronous mirror delay circuit includes a clock buffer circuit 10, a delay monitor circuit (DMC) 12, a forward delay array (FDA) 14, a mirror control circuit (MCC) 16, a backward delay circuit (BDA) 18, a clock driver 20, and a dummy load 22.
The clock buffer circuit 10 receives an external clock signal CLKext to generate an input clock signal CLKin having one-shot pulse shape. The input clock signal CLKin is delayed for a delay time of “Td1” by the clock buffer circuit 10. The delay monitor circuit 12 delays an input clock signal CLKin from the clock buffer circuit 10 for a delay time of “Td1+Td2”. The forward delay array 14 has a plurality of serially-connected delay units FD1-FDn and outputs a plurality of delayed clock signals FDA1-FDAn. The delay units FD1-FDn are controlled by the mirror control circuit 16, as shown in FIG. 1. Each of the delay units FD1-FDn is set to have the same delay time, and comprises a NAND gate and an inverter. The mirror control signal 16 includes a plurality of phase detectors PD1-PDn each receiving an input clock signal CLKin from the clock buffer circuit 10 and a delayed clock signal FDAi from a corresponding delay unit FDi in the forward delay array 14. The phase detector PDi (i=1−n) detects whether the inputted clock signals CLKin and FDAi have the same phase. That is, the mirror control circuit 16 detects a delayed clock signal FDAi delayed for one cycle relative to an input clock signal CLKin from the clock buffer circuit 10, i.e., the delayed clock signal FDAi having a phase difference of one cycle. This means a delay time of the forward delay array 14 becomes “Tclk−(Td1+Td2)”. The backward delay array 18 includes a plurality of serially-connected delay units BD1-BDn. The delay unit BDi (i=1−n) is set to have the same delay time as the delay unit FDi of the forward delay array 14, and comprises a NAND gate and an inverter. The clock driver 20 delays a clock signal BDAout from the backward delay array 18 for a delay time of the “Td2” to generate an internal clock signal CLKint. The internal clock signal CLKint has the same phase as the external clock signal CLKext. The dummy load 22 is added to make symmetrical the forward delay array 14 and the mirror control circuit 16 to the backward delay array 18 and the dummy load 22.
The operation of the prior art synchronous mirror delay circuit is now described with reference to FIG. 2A through FIG. 2F.
When a clock signal CLKext shown in FIG. 2A is externally inputted, the clock buffer circuit 10 generates an input clock signal CLKin shown in FIG. 2B. The input clock signal CLKin is delayed for a delay time of “Td1” by the clock buffer circuit 10. Next, the delay monitor circuit 12 delays the input clock signal CLKin for a delay time of “Td1+Td2”. A clock signal FDAin shown in FIG. 2C is inputted to the forward delay array 14. The forward delay array 14 sequentially delays the clock signal FDAin through the delay units FD1-FDn. The mirror control circuit 16 compares the input clock signal CLKin with each of delayed clock signals FDA1-FDAn to generate pulse signals at an instant where input clock signals have the same phase. For example, assuming that one of pulse signals from the mirror control circuit 16 has a low level, and the others have a high level, the mirror control circuit 16 detects a delayed clock signal FDAi (having a phase difference of one cycle) that is delayed for one cycle relative to an input clock signal CLKin from the clock buffer circuit 10. The detected delayed clock signal FDAi is outputted as an internal clock signal CLKint through the backward delay array 18 and the clock driver 20.
The following equation exhibits the total time required for phase-synchronizing an external clock signal CLKext and an internal clock signal CLKint.T—tot=Td1+(Td1+Td2)+2{Tclk−(Td1+Td2)}+Td2=2Tclk   [Equation 1]
In the equation, “Td1” represents a delay time of the clock buffer circuit. “Td1+Td2” is a delay time of a delay monitor circuit 12. “Tclk−(Td1+Td2)” represent a delay time of forward/backward delay arrays 14 and 18 at the time when an input signal CLKin provided to the mirror control circuit 16 is phase-synchronized with a clock signal passing the forward delay array 14. “Td2” represents a delay time of the clock driver 20. Given the equation above, the internal clock signal CLKint is synchronized with the external clock signal CLKext at two cycles. That is, the internal clock signal CLKint is synchronized with an (N+2)th external clock signal CLKext based on an Nth external clock signal CLKext, as shown in FIG. 2. As a result, after an external clock signal CLKext is inputted, an internal clock signal CLKint synchronized with the external clock signal CLKext is generated.
Generally, factors affecting performance of a synchronous mirror delay circuit include jitter and locking range. The jitter of the synchronous mirror delay circuit means a time error between an external clock signal CLKext and an internal clock signal CLKint, and has a value within a delay time of each delay unit in the delay arrays 14 and 18. The synchronous mirror delay circuit is an open-loop-shaped delay line, having a jitter resolution within one delay unit. The locking range of the synchronous mirror delay circuit means a range where a delayed clock signal FDAi synchronized with an input clock signal CLKin is detected through the forward delay array 14.
In general, the locking range correlates with jitter in view of delay units. For example, where the locking range is sought to increase with delay units unchanged in number, jitter is increased. Thus, to increase the locking range with jitter unchanged, the delay units have to increase in number. There is usually such a trade-off between jitter and locking range.
For more detail, the synchronous mirror delay circuit having a locking range of “Tclk−(Td1+Td2)” is shown in FIG. 1 and FIG. 2. To widen the locking range thereof, a value of “Tclk−(Td1+Td2)” should be increased by decreasing “Td1” and “Td2”. However, to keep jitter unchanged, the delay units should increase in number.
On the other hand, where jitter is sought to reduce with the locking range unchanged, a jitter resolution must be increased using more delay units. This is because jitter has a value within the time of a delay unit. A need therefore exists for a synchronous mirror delay circuit having an adjustable locking range.